1. Field of the Invention
The present invention relates to a divider, and more particularly, to a clock divider.
2. Background of the Related Art
FIG. 1 is a configuration block of a conventional clock divider using a ripple carry counter. FIG. 2 shows operational waveforms of a conventional clock divider using a ripple carry counter. As shown, the transition of output values from respective flip-flops 1a, 1b, 1c and 1d occurs at negative edges of input clock signals clk-in. The output values of the respective flip-flops 1a, 1b and 1c are respectively provided to an adjacent flip-flop.
A clock divider using an MOD-N counter has an output value "0" for a prescribed number of input clock cycles and then has an output value "1" for the prescribed number of input clock cycles. For example, if the input clock signal has a clock period of 100 ns (frequency of 10 MHZ) and an output clock signal having a period of 1600 ns is desired, the clock divider has an output value "0" for eight (8) complete cycles of the input clock signal and has an output value of "1" for the next eight (8) complete cycles of the input clock signal. The MOD-N counter is a ripple counter having the number of states N. In the case that the ripple counter includes M number flip-flops M, the relationship between the flip-flops and the number N can be expressed as N=2.sup.M.
Since the conventional clock divider as aforementioned generates clocks having an even number of cycles from reference clocks (input clocks), it is difficult to generate an output clock signal having an odd number of cycles of the input clock signal. In addition, the conventional clock divider fails to realize a duty cycle of about 50% or less to generate the output clock signals having an odd number of cycles even if it is possible to do so. For this reason, the conventional clock divider has a problem that it is not suitable for systems which require clocks of different odd number of cycles or periods with a duty cycle of about 50%.